Optimization of memory bandwidth in a multi-display system
US8471860B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2012 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jul 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/022
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.