Validation of a print verification system
US8472073B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2005 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jan 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30144
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and media are disclosed for testing the accuracy of a print verification system (PVS) in test mode, wherein a PVS is often used to validate the accuracy of printed output. One embodiment includes receiving, by an application, an output from a print verification system associated with the application, wherein the output comprises one or more defects. The embodiment also includes receiving, by the application, a list, such as a copy, of seeded defects for the output, wherein the list is uploaded to and saved by the application. In addition, the embodiment includes matching, by the application, the one or more seeded defects in the list that correspond to the one or more defects in the output. Finally, the embodiment includes displaying, by the application, results of the testing after the matching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.