System and method for de-latch of an integrated circuit
US8472276B1 · kind B1 · utility
1Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Dec 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided for hot de-latch of a parasitic device in an integrated circuit (IC) that restores the IC to normal operation without de-powering the IC or resulting in a loss of data. In one embodiment the method, includes reducing a voltage supplied to at least a portion of the IC from a normal operation voltage to a de-latch voltage for a time to de-latch the parasitic device without de-powering the IC. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.