Memory device and wear leveling method
US8473668B2 · kind B2 · utility
12Cited by
0References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 18, 2009 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jul 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.