Memory device and memory system comprising same
US8473694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Aug 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.