Multi-chip memory system and related data transfer method
US8473811B2 · kind B2 · utility
8Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 2, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Sep 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip memory system comprises source and target memory devices, a memory controller configured to control operations of the source and target memory devices, and a data bus configured for data transfer of the memory controller and the source and target memory devices. The memory controller controls the source memory device to perform a read operation to output data to the data bus. Concurrently, the memory controller controls the target memory device to store the data from the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.