Method and system for error correction in flash memory
US8473812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Apr 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/563
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate a series of encoded data bits, and converts the series of encoded data bits into a series of data symbols. The controller sends, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array. The controller generates an output signal based on data associated with the stored series of data symbols. The output signal is characterized by a second number of digital levels greater than the first number of digital levels. The controller outputs a series of output data symbols based on the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.