Method and apparatus for automatically fixing double patterning loop violations
US8473874B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Aug 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG21K5/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both edges to resolve the violation. The method of some embodiments computes the cost of applying each design solution to the IC design layout and prioritizes the generated solutions for all the identified pairs of edges based on the computed cost for each solution. The method in some embodiments then selects a solution from the prioritized solutions and applies the selected solution to the design layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.