Patent · US Active

Memory device and fabrication process thereof

US8476614B2 · kind B2 · utility

8Cited by

2References

6Claims

0Family size

Assignee

SONY GROUP CORPORATION · JP

Inventors

Jun Sumino · Boise, US
Shuichiro Yasuda · Boise, US

Key dates

Filing date	Oct 18, 2010
Grant date	Jul 2, 2013
Priority date	—
Expiry date	Oct 27, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C13/0002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory device that includes a resistive-change memory element, the memory device includes: a first memory element that includes a first resistive-change layer and a first electrode connected to the first resistive-change layer; and a second memory element that includes a second resistive-change layer and a second electrode connected to the second resistive-change layer, wherein at least one of the thickness and the material of the second resistive-change layer and the area of the second electrode in contact with the second resistive-change layer is different from the corresponding one of the thickness and the material of the first resistive-change layer and the area of the first electrode in contact with the first resistive-change layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.