Thin film transistor array substrate for a display panel and a method for manufacturing a thin film transistor array substrate for a display panel
US8476633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2009 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Jan 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate. Over the above multi-layers of the passivation film forming a first photoresist pattern comprising a first portion formed on part of the drain electrode and on the pixel region, and a second portion wherein, the second portion thicker than the first portion, and then patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern; and forming a transparent electrode pattern on the second passivati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.