Stress reduced cascoded CMOS output driver circuit
US8476940B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2011 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Dec 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.