Patent · US Active

Reduced area schmitt trigger circuit

US8476948B2 · kind B2 · utility

1Cited by

5References

15Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventor

Rajeev Jain · Greater Noida, IN

Key dates

Filing date	Nov 6, 2009
Grant date	Jul 2, 2013
Priority date	—
Expiry date	Aug 19, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/3565
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.