Low noise memory array
US8477526B2 · kind B2 · utility
5Cited by
8References
20Claims
0Family size
Inventor
Key dates
| Filing date | Jun 3, 2012 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Jun 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (700) having a first bit line (754) extending in a first direction and a second bit line (752) extending in a second direction parallel to the first bit line. A second sense amplifier (704) has a third bit line (756) adjacent and parallel to the first bit line. The third bit line remains inactive while the first bit line is active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.