Packet processing apparatus for realizing wire-speed, and method thereof
US8477626B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Jan 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Provided are a packet processing apparatus for realizing a wire-speed, and a method thereof. The packet processing apparatus realizes a wire-speed by making an inputted packet be processed in another packet processing apparatus instead of processing the inputted packet for itself. The packet processing apparatus for realizing a wire-speed by having an inputted packet processed in a packet processor of another packet processing apparatus by making an inputted packet detour a packet processor into a detour path, includes: a packet classifier for classifying and storing the inputted packet in a multi-queue based on a priority; a queue manager for including the multi-queue, determining a detour packet among packets stored in the multi-queue and marking the packet as a detour packet; and a packet scheduler for transmitting the packet designated as the detour packet to the detour path. The apparatus is used for a packet communication system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.