Pairing computation device, pairing computation method and recording medium storing pairing computation program
US8477934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2010 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Apr 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3073
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
There is provided a pairing computation device provided with a CPU which computes pairing e(S,Q) with SεG1, QεG2, χ being a given integer variable, and F being a rational function calculated using Miller's algorithm with respect to multi-pairing (MMA). An order r, a trace t of the Frobenius endomorphism φp are specified preliminarily using the integer variable χ according to an embedding degree k. The CPU performs pairing computation by means of: an input unit which inputs the integer variable χ, the rational point S, and the rational point Q into respective predetermined registers; a computation unit which computes F; a computation unit which computes a value at a rational point Q(xQ, yQ) of a straight line passing through given rational points; a computation unit which computes f′ χ,S(Q) using the aforementioned F and the value; and a computation unit which computes the pairing e(S,Q) using aforementioned f′ χ,S(Q) as [F83].[F83]e(S,Q)=f′χ,S(Q)(p−1)/r.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.