Gather and scatter operations in multi-level memory hierarchy
US8478941B2 · kind B2 · utility
11Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2012 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Jul 24, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.