Dynamic management of destage tasks in a storage controller
US8478945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2010 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Feb 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method, system, and computer program product embodiments for facilitating data transfer from a write cache and NVS via a device adapter to a pool of storage devices by a processor or processors are provided. The processor(s) adaptively varies the destage rate based on the current occupancy of the NVS for a particular storage device and stage activity related to that storage device. The stage activity includes one or more of the storage device stage activity, device adapter stage activity, device adapter utilized bandwidth and the read/write speed of the storage device. These factors are generally associated with read response time in the event of a cache miss and not ordinarily associated with dynamic management of the destage rate. This combination maintains the desired overall occupancy of the NVS while improving response time performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.