Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts
US8479131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2011 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.