Efficient and self-balancing verification of multi-threaded microprocessors
US8479173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2008 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | May 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Creating one or more irritator threads on one or more processor cores in a multi-threaded multiprocessor data processing system is provided. A test generator generates non-irritator thread code for execution by a non-irritator thread and irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system. A simulation controller instantiates the non-irritator thread to execute the non-irritator thread code and the one or more irritator threads to execute the irritator thread code. The simulation controller determines if the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code. Responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, the non-irritator thread performs an operation to terminate the execution of the irritator thread code by the one or more irritator threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.