Register mapping techniques for efficient dynamic binary translation
US8479176B2 · kind B2 · utility
28Cited by
14References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2010 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Apr 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45525
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generally, the present disclosure provides a system and method for mapping registers from a system with more registers to a system with fewer registers. Regions may be formed that include one or more blocks of code with relatively frequent register accesses. The most frequently accessed source registers may be mapped to target registers. Each block in the region may be bounded by a prologue and at least one epilogue. The prologue may be configured to implement register mapping and the epilogue(s) may be configured to manage program flow from a block in the region to another block in the region or to a block not in the region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.