Compiling method, compiling apparatus and computer system for a loop in a program
US8479179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2005 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Dec 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for compiling a program including a loop is provided. In the program, the loop includes K instructions (K>2) and repeats for M times (M>2). The compiling method comprises following steps: performing resource conflict analysis to the K instructions in the loop; dividing the K instructions in the loop into a first combined instruction section, a connection instruction section and a second combined instruction section, wherein there is no resource conflict between the instructions in the first combined instruction section and the instructions in the second combined instruction section respectively; and compiling the program, wherein the instructions in the first combined instruction section in the cycle N (N=2, 3, . . . M) and the instructions in the second combined instruction section in the cycle N−1 are combined to be compiled respectively. A compiling apparatus and a computer system for realizing the above-mentioned compiling method are further provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.