Patent · US Active

Processor with hardware solution for priority inversion

US8479201B2 · kind B2 · utility

0Cited by

5References

13Claims

0Family size

Assignee

INNOVASIC, INC. · US

Inventors

Volker Ewald Goller · Aachen, DE
Andrew David Alsup · Albuquerque, US

Key dates

Filing date	Sep 18, 2006
Grant date	Jul 2, 2013
Priority date	—
Expiry date	Mar 20, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/462
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts is provided. The method comprises: providing a plurality of context control registers with each context control register being associated with a corresponding one context for controlling execution of the context; providing a plurality of sets of hardware registers, each set corresponding to one context of the plurality of contexts; and utilizing the plurality of context control registers and said plurality of sets of hardware registers to prevent priority inversion.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.