Nanocrystal memories and methods of forming the same

US8481386B2 · kind B2 · utility

Assignee

• The Regents of the University of California · US

Inventors

• Jianlin Liu · Los Angeles, US
• Dengtao Zhao · San Jose, US
• Yan Zhu · Beijing, CN
• Ruigang Li · Austin, US
• Bei Li · Redwood City, US

Key dates

• Filing date: Apr 9, 2010
• Grant date: Jul 9, 2013
• Expiry date: Apr 26, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

In one embodiment, a memory device includes a substrate, a tunneling oxide, a silicide nanocrystal floating gate, and a control oxide. The tunneling oxide is positioned upon a first surface of the substrate, the silicide nanocrystal floating gate is positioned upon the tunneling oxide, and the control oxide positioned upon the nanocrystal floating gate.