Patent · US Active

Trap rich layer with through-silicon-vias in semiconductor devices

US8481405B2 · kind B2 · utility

80Cited by

17References

19Claims

0Family size

Assignee

IO Semiconductor, Inc. · US

Inventors

Anton Arriagada · San Diego, US
Chris Brindle · Poway, US
Michael A. Stuber · Carlsbad, US

Key dates

Filing date	Oct 15, 2012
Grant date	Jul 9, 2013
Priority date	—
Expiry date	Oct 15, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/9202
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.