Memory and interconnect design in fine pitch
US8482039B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Sep 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory array includes a first layer, a second layer, a third layer and a contact. The first layer is disposed on a substrate. The second layer includes a first conductive line. The first conductive line includes first line segments and second line segments. Each of the second line segments are connected to a respective one of the first line segments. The first line segments extend in a first direction on the first layer. The second line segments extend in a second direction on the first layer. The first direction is different than the second direction. The third layer is disposed on the second layer. The contact is disposed through the second layer and connects the third layer to the first conductive line. One of the first line segments extends towards the contact. Each of the first and second line segments are at least a predetermined distance from the contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.