Circuit for controlling PSON signal
US8482324B2 · kind B2 · utility
1Cited by
1References
14Claims
0Family size
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Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Apr 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.