High voltage input receiver with hysteresis using low voltage transistors
US8482329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2008 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Dec 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.