Robust SRAM memory cell capacitor plate voltage generator
US8482964B2 · kind B2 · utility
0Cited by
2References
15Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 22, 2009 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.