Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model
US8484007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2008 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Sep 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.