Processing array data on SIMD multi-core processor architectures
US8484276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2009 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Mar 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists of a sequence of blocks, where each block interleaves s rows such that SIMD vector processors may operate on s rows simultaneously. As a result, the converted data in SIMD format enables smaller-sized 1D FFTs to be optimized in SIMD multi-core processor architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.