Radiation-hardened processing system
US8484509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2010 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Jun 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.