System and method for consecutive identical digit reduction
US8484518B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2009 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Feb 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4908
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data transmission network, such as a passive optical network, the consecutive identical digit (CID) handling requirements may be reduced by providing a CID monitoring module at the transmitter end that monitors the number of CIDs in a transmission stream. Where the CID number exceeds a threshold, an error generation module induces an error in the transmission stream to reduce the CID below the threshold. The modified transmission stream may then be transmitted to a receiver, allowing clock recovery be performed with improved stability at the receiver. Once clock recovery is achieved, the receiver can then process the transmission stream to correct the errors induced at the transmitter end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.