Error correction and detection in a redundant memory system
US8484529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2010 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Apr 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.