Optimizing cell libraries for integrated circuit design
US8484601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2011 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Aug 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.