Power semiconductor device

US8487374B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Hiroshi Ohta · Wako, JP
• Yasuto Sumi · Himeji, JP
• Kiyoshi Kimura · Amuru, UG
• Junji Suzuki · Nagoya, JP
• Hiroyuki Irifune · Kasai, JP
• Wataru Saito · Yokohama, JP
• Syotaro Ono · Yokohama, JP

Key dates

• Filing date: Sep 16, 2011
• Grant date: Jul 16, 2013
• Expiry date: Jan 13, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/111

Abstract

In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.