Chip stack with conductive column through electrically insulated semiconductor region
US8487422B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Aug 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.