Device for generating clock signals for asymmetric comparison of phase errors

US8487676B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE · FR
• Universite Pierre Et Marie Curie (Paris 6) · FR

Inventors

• Eric Colinet · Bois-Guillaume, FR
• Dimitri Galayko · Lille, FR
• Anton Korniienko · Val-de-Reuil, FR

Key dates

• Filing date: Oct 28, 2010
• Grant date: Jul 16, 2013
• Expiry date: Oct 28, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L2207/50
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A device for generating a clock signal, including a phase-locked loop including: a controlled oscillator to deliver a clock signal; plural phase comparators to compare a phase of the clock signal delivered by the controlled oscillator with plural clock signal phases applied at an input of the phase-locked loop; a mechanism for weighted summation of output signals of the plural phase comparators such that one or more of the weighting coefficients applied to one of the output signals has an absolute value that overrides the absolute values of the other weighting coefficients applied to the other output signals; and a mechanism filtering the weighted sum of the output signals of the plural phase comparators, to deliver at an output a control signal to the controlled oscillator.