Half cycle delay locked loop
US8487678B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2011 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Oct 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also includes N delay elements outputting N different phase-shifted signals, where a total delay introduced by the N delay elements is M/2. The integrated circuit also includes a plurality of inverters, each coupled to an output of one of the N delay elements, where the plurality is less than N. The integrated circuit also includes a phase detector coupled to the input node and an inverted Nth phase-shifted signal. The integrated circuit also includes a charge pump coupled to the phase detector and the delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.