Patent · US Active

Multi-phase clock generator

US8487682B2 · kind B2 · utility

5Cited by

0References

21Claims

0Family size

Assignee

Initio Corporation · US

Inventors

Zhenchang Du · Hangzhou City, CN
Haiming Tang · Cupertino, US
Wei Wang · Beijing, CN

Key dates

Filing date	Aug 11, 2011
Grant date	Jul 16, 2013
Priority date	—
Expiry date	Oct 11, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00052
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.