Stacked linear power amplifier with capacitor feedback and resistor isolation
US8487706B2 · kind B2 · utility
132Cited by
50References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 25, 2010 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Oct 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and/or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.