Method of gain calibration of an ADC stage and an ADC stage
US8487792B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2009 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Nov 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0641
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of gain calibration of an ADC stage is provided. The method includes steps of receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The the calibration signal may take any one of three values and may be constrained to one of only two of these three values. An ADC stage adapted to operate according to the method is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.