Flash memory device and method of operation
US8488389B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2011 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Sep 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.