Latency rate distortion optimisation
US8488673B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2009 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Feb 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/593
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method of improving latency in a Rate Distortion Optimization apparatus, comprising re-ordering processing of a sequence of 4×4 blocks of pixels received for processing by the Rate Distortion Optimization apparatus, the received order of the 4×4 blocks of pixels corresponding to the location of the 4×4 blocks of pixels within a macroblock, and processing the re-ordered sequence of 4×4 blocks in the Rate Distortion Optimization apparatus, where the re-ordering of the processing of the 4×4 blocks of pixels comprises interleaving the processing of two upper 4×4 blocks of pixels of a current 8×8 block with the processing of two lower 4×4 blocks of pixels of a previous 8×8 block. There is also provided a method of improving latency in a Rate Distortion Optimization apparatus, where the Rate Distortion Optimization apparatus assesses nine intra prediction modes and the method further comprises re-ordering processing of intra prediction modes such that a first six modes processed are not dependent on a block of pixels above and to the right of a current block of pixels, and processing the re-ordered sequence of intra prediction modes in the Rate Distortion Optimization…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.