Increasing memory capacity of a frame buffer via a memory splitter chip
US8489839B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2009 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Dec 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The memory splitter chip couples multiple DRAM units to the PPU, thereby expanding the memory capacity available to the PPU for storing data and increasing the overall performance of the graphics processing system. The memory splitter chip includes logic for managing the transmission of data between the PPU and the DRAM units when the transmission frequencies and the burst lengths of the PPU interface and the DRAM interfaces differ. Specifically, the memory splitter chip implements an overlapping transmission mode, a pairing transmission mode or a combination of the two modes when the transmission frequencies or the burst lengths differ.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.