Method of selective power cycling of components in a memory device independently by reducing power to a memory array or memory controller
US8489907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2009 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Jul 16, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.