Circuits and methods for processors with multiple redundancy techniques for mitigating radiation errors
US8489919B2 · kind B2 · utility
30Cited by
17References
39Claims
0Family size
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Key dates
| Filing date | Nov 25, 2009 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Jan 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.