Shuffled LDPC decoding
US8489962B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2008 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | May 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means (1010) compute for a next iteration symbol messages λκm from a representation of a corresponding symbol value stored in a first memory 1005 and from check node messages Λmn from a previous iteration. A shuffler (1030) changes a sequence of the symbol message received from the first computation means (1010) in dependence on a position of the non-zero elements in a corresponding sub-matrix. Second computation means (DP-O, DP-I, DP-D-I) compute the check node messages in dependence on symbol messages received from the barrel shifter and store a representation of the computed check node message in a second memory (1015). Third computation means (1020) update the representation of the symbol values in the first memory in dependence on output of the first and second computing means. The principle of “staggered” or “shuffled” LDPC decoding is used. One embodiment is designed for multi-diagonal circulants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.