On-chip inductors with through-silicon-via fence for Q improvement
US8492872B2 · kind B2 · utility
6Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2007 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Sep 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.