Architecture and technique for inter-chip communication
US8493300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2008 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B45/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention involves an electrical system in which an analog signal channel passes through various integrated circuit chips (ICs). The channel can carry one or more analog signals. Each IC can modify the signal(s) passing through it and pass it on to another IC or system component. The channel can be programmable. Each IC can include a comparator or a multiplexor to receive the channel signal from another IC or system component and to modify the received signal before transmitting it to another IC or system component. The comparator or the multiplexor can be programmable and can be selectively configured to compare the incoming signal from the channel with a variety of other signals and thresholds, or to simply act as a flow through gate and allow the signal to pass without any modification. The comparison can determine the output of the comparator. The operation and programming of the comparators, the multiplexors and the channel can be centrally controlled by a system controller, can be independently controlled by the ICs, or a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.