State machine control for a pipelined L2 cache to implement memory transfers for a video processor
US8493397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Apr 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/86
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.